The present invention relates to the fabrication of integrated circuits. More particularly, the invention provides a technique, including a method and apparatus, for the deposition of a high-quality fluorine-doped insulating film having a reduced dielectric constant.
Semiconductor device geometries continue to decrease in size, providing more devices per fabricated wafer and faster devices. Currently, some devices are being fabricated with less than 0.25 .mu.m spacing between features; in some cases there is as little as 0.18 .mu.m spacing between device features. An example of these features are conductive lines or traces patterned on a layer of metal. A nonconductive layer of dielectric material, such as silicon dioxide, is often deposited between and over the patterned metal layer. This dielectric layer may serve several purposes, including protecting the metal layer from physical or chemical damage, insulating the metal layer from other layers, and insulating the conductive features from each other. As the spacing, or gap, between these conductive features decreases, it becomes more difficult to fill that gap with the dielectric material.
Processing wafers with aluminum traces requires keeping the temperature of the wafer below where damage may occur to the aluminum. The aluminum may be damaged by melting or by chemical attack, including the formation of aluminum compounds. Chemical vapor deposition (CVD) typically requires elevated temperatures to induce the reactions necessary to form a layer. Various methods are used to lower the deposition temperature. Some methods focus on using highly reactive deposition gases. Other methods apply electromagnetic energy to the deposition system. Applying electromagnetic energy can both lower the temperature necessary for reaction of the deposition gases and can improve the formation of a deposited layer by moving reactant species relative to the growing layer.
Many approaches to obtain lower dielectric constants and to fill gaps with dielectric material have been proposed. One of the more promising solutions is the incorporation of halogen atoms into a silicon dioxide layer. Examples of halogen incorporation in films are described in U.S. patent application Ser. No. 08/548,391, filed Oct. 25, 1995 and entitled "METHOD AND APPARATUS FOR IMPROVING FILM STABILITY OF HALOGEN-DOPED SILICON OXIDE FILMS", and Ser. No. 08/538,696, filed Oct. 2, 1995 and entitled "USE OF SIF.sub.4 TO DEPOSIT F-DOPED FILMS OF GREATER STABILITY", both of which are assigned to Applied Materials, Inc.
It is believed that fluorine, the preferred halogen dopant for silicon oxide films, lowers the dielectric constant of the silicon oxide film because fluorine is an electronegative atom that decreases the polarizability of the overall SiOF network. Fluorine-doped silicon oxide films are also referred to as fluorinated silicon glass (FSG) films.
In addition to decreasing the dielectric constant, incorporating fluorine in silicon dioxide layers can also improve the gap-filling properties of the deposited films. Because fluorine is an etching species, it is believed that fluorine etches the film as it is being deposited. This simultaneous deposition/etching effect preferentially etches the corners of the gap, keeping the gap open so that it fills with void-free FSG.
Unfortunately, there are several problems associated with some FSG layers. One problem is that a poorly formed FSG layer may absorb moisture from the atmosphere, or from the reaction products associated with the deposition process. The absorption of water raises the dielectric constant of the FSG. Absorbed water may also interfere with subsequent wafer processing steps. For many applications, it is desirable that FSG layers do not desorb significant water vapor below about 450.degree. C.
One technique that is used to reduce water absorption and desorbtion is to bake the wafer after the FSG layer has been deposited. Baking may be done in the same chamber, immediately after depositing the FSG, or it may be done afterwards in an oven. Baking may drive off some of the water in the FSG layer, but the layer may reabsorb water from the atmosphere under some circumstances. For example, water reabsorption may not be a problem if wafer processing continues fairly soon after the FSG deposition and bake. However, in some manufacturing environments, wafer processing subsequent to the FSG deposition may not occur for days or even weeks, thus potentially providing conditions for water reabsorption. Time between wafer processing steps may arise because of work-in-process queuing, distributed manufacturing (i.e., one process step is performed in one factory location, and a subsequent processing step is performed in another factory location), or delays due to equipment maintenance, etc.
Cap layers provide one method of reducing reabsorption of water into an FSG layer. The cap layer is typically undoped silicon glass (USG) layer that is deposited onto an FSG layer with or without baking the FSG layer prior to depositing the cap. The cap may be done in a separate deposition chamber or pump-down, or the process may be streamlined to follow the FSG layer deposition in the same chamber. Cap layers may provide acceptable protection from water absorption under many conditions. However, adding a cap layer adds time to the wafer fabrication process. In some instances, for example where the total layer deposition time is fairly long, the time to add a cap layer is not significant. As wafer throughput (the number of wafers processed in a deposition chamber per hour) increases, the cap layer deposition time may become a significant portion of the total deposition time. In those instances, it may be desirable to reduce the total layer deposition time by eliminating the step of depositing a cap layer.
Corrosion is another problem associated with some FSG layers. If fluorine is loosely bound into the FSG lattice, or has accumulated as free fluorine on the surface, it may combine with water to form hydrofluoric acid (HF). HF may corrode, and even destroy, other device features such as metal traces or antireflective layers.
One technique that is used to overcome the problems of corrosion is to form a liner over the wafer before depositing the FSG. The liner is typically a thin layer of USG that acts as a barrier between device features and the FSG. A thicker liner will perform this function better. Because the liner is made of USG, it has a higher dielectric constant than the FSG layer, and a thinner liner is desired to maintain a low dielectric constant for the layer between conductive traces. The best liner thickness is a compromise between corrosion protection and low dielectric constant for the layer. As with baking and cap layers, it is desirable to form any liner in as short a time as possible to reduce the process time.
A further problem with some FSG layers is that they are unstable. In other words, the layer characteristics change over time. For example, poorly formed FSG layers may form a cloudy haze, or even bubbles, within the layer when exposed to the atmosphere. A wafer exposed to relatively dry air for a short period of time may not develop any haze, whereas the same wafer exposed to wetter air for the same period, or dry air for a longer period of time, will develop haze. Modern device fabrication often uses distributed processing, where a wafer is processed at several different locations over a period of several weeks. Wafers that develop haze are typically rejected from the processing sequence, losing the value of all the materials and processing to that point of the production sequence. Under some manufacturers' specifications, it is important that such wafers do not develop haze when exposed to the atmosphere for a period of at least three weeks.
Hazing is a subtle and difficult problem. Even the bulk resistivity of the wafer may affect a wafer's propensity to form haze. Haze formation may be related to the temperature of the wafer during deposition, which may affect how water and fluorine are incorporated into the layer. Some processing chambers use an electrostatic chuck (e-chuck) to hold the wafer in place during processing. Wafer resistivity may contribute to how strongly the wafer is held, and thus how well it thermally couples to the e-chuck. Whatever the mechanism of haze formation is, wafer resistivity adds another variable into the wafer fabrication sequence that may constrain the process flow and decrease yields.
Furthermore, speaking generally, the higher the concentration of fluorine during deposition of the FSG layer, the greater the propensity to form haze. Therefore, chip manufacturers may use a relatively low concentration of fluorine just to avoid the potential haze-forming problem. If manufacturers could rely on producing a more stable FSG film, they could increase the fluorine concentration and enjoy the resultant benefit of an FSG layer with a lower dielectric constant.
From the above, it can be seen that it is desirable to produce oxide films having reduced dielectric constants and good gap-fill properties in the shortest time possible. It is also desirable to provide a method of increasing the stability of halogen-doped oxide films, thereby reducing moisture absorption and hazing in the films, regardless of wafer resistivity.